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Innovative Algorithm for Wide Band Digital Signal Processing in modern AESA RADAR Architecture
RF sampling technology, already available in L,S and C bands, allows acquiring the whole operative RADAR bandwidth. In this context, to overcome digital processing bottlenecks, an innovativeFPGA based algorithm, targeting wide band RADAR signal has been designed. The algorithm is able to digitally process wide band signals, with a FPGA operative clock frequency much lower than the one requested by standard Nyquist-basedprocessing. The same algorithm can also be used to reduce the FPGA operating clock frequency and therefore power consumption, a burning issue for small form factor modules. The algorithm is characterized in terms of functionalities, performance and FPGA implementation; an actual case study is presented
Lalli Roberto, Rapisarda Caterina¸ Manuale Alessandro, Tocca Valerio
Paper for Seminar/Symposium/Conference
EDI CON 2017 - Electronic Design Innovation Conference & Exhibition (11-13 September 2017, Boston, USA)
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